1. Field of the Invention
The present disclosure relates to an amplifier circuit and a controlling method thereof.
2. Description of Related Art Including Information Disclosed Under 37 CFR 1.97 and 37 CFR 1.98
With the development of the wireless communication system developing from the second generation (2G) wireless network, to the third generation (3G) wireless network, to the new fourth generation (4G) wireless network, a big challenge that portable system designers encounter is to design a system supporting numerous wireless communication standards including the global system for mobile communications (GPRS), general packet radio service (GPRS), enhanced data rates for global evolution (EDGE), code division multiple access (CDMA), wideband CDMA (WCDMA) and wireless fidelity (Wi-Fi), such as IEEE 802.11 and the related standards. Also, the communication systems using a 4G topology require capability to operate in multiple frequencies and multiple modes and support of a multiple-input multiple-output (MIMO) antenna structure. However, the power source of most portable systems is a battery. Therefore, with the trend toward design of more complicated circuits and increasing number of devices, integrating modules in a system to a single chip and increasing battery lifetime are becoming important issues in portable system design.
In a portable wireless communication system, a baseband processor and a radio frequency receiver can now be integrated into a single chip. However, a radio frequency (RF) power amplifier (PA), which consumes the most power in the chip, is implemented by gallium-arsenide (GaAs) technology, and thus it cannot be integrated in the single chip. The known semi-insulative property of the GaAs material can largely reduce parasitic resistance in the base, making the GaAs material well-suited for the application of high frequency circuits. However, GaAs technology exhibits relatively low yields and high costs in manufacturing. In addition, such technology cannot implement a system-on-chip structure. Therefore, with the recent improvement of the CMOS technology, more and more chip designers are attempting to design RF power amplifiers by the CMOS technology.
The considerations in the design of an RF power amplifier in general are the linearity and the power efficiency. In general, the power efficiency is maximum when the RF power amplifier operates in or near the saturation region. However, in order to modulate an RF signal having an inconsistent envelope, the RF power amplifier usually operates at several dB of back-off out power from 1 dB gain compression point or peak power so as to insure it works at the linear region. The RF power amplifier operated in the linear region has lower power efficiency, and thus suffers from reduced battery life of the portable system.
The factors causing the non-linearity of the power amplifier in general are the even-order harmonic and odd-order harmonic, wherein the even-order harmonic includes a second-order harmonic, which is usually the primary portion of the total harmonic distortion. FIG. 1 shows a block diagram of a conventional RF power amplifier 10 configured to suppress the second-order harmonic. Referring to FIG. 1, an input signal from an input terminal 11 is split through an input balun 12 into two signals S1 and S2, each having equal power and phase difference of 180 degrees with respect to each other. Signals S1 and S2 are transmitted to first and second input matching circuits 13 and 14, respectively, to obtain impedance matching, and then transmitted to first and second amplifiers 15 and 16, respectively. Next, the output signals of the first and second amplifiers 15 and 16 are transmitted to first and second output matching circuits 17 and 18, respectively, to obtain impedance matching, and transmitted to an output balun 19. The split signals S1 and S2 are combined in phase via the output balun 19 and the combined signal is outputted from an output terminal 20. Referring to FIG. 1, the conventional RF power amplifier 10 requires two baluns 12 and 19 to split and combine a signal.
US publication No. 2006/0049876 discloses an active circuit 22 having improved linearity using multiple gated transistors, wherein the active circuit 22 is a common gate circuit. Referring to FIG. 2, the active circuit 22 comprises a main circuit 24 and an assistant circuit 26. The main circuit 24 comprises a transistor M1 and a capacitor CA, and the assistant circuit 26 comprises a transistor M2 and a capacitor CB. The third-order harmonic of the active circuit 22 is suppressed via the assistant circuit 26; however, the second-order harmonic of the active circuit 22 requires an additional balun to be suppressed.
A conventional balun occupies a large chip area, and the power consumption of the balun reduces the overall efficiency of the chip. Therefore, it is desirable to provide an amplifier circuit having improved linearity and to provide a design for improving the power efficiency of the amplifying circuit and for increasing the battery life.